The present invention relates to ferroelectric memory devices, and particularly to memory cells and memory array architectures making use of junction-isolated ferroelectric depletion-mode field-effect transistors.
Ferroelectric materials are a class of materials that can be thought of as having electrical properties somewhat analogous to the magnetic properties of ferromagnetic materials. A uniaxial ferromagnetic material can be magnetized in one of two directions, and thereafter will retain a magnetic field in that direction even after the applied magnetic field is removed; similarly, a ferroelectric material can be xe2x80x9cpolarizedxe2x80x9d in either direction (by applying an electric field to it), and thereafter will retain an electric field in that direction, even after the applied electric field is removed.
Ferroelectric materials have been successfully integrated into integrated circuit processes, but this integration can have some drawbacks. Ferroelectric materials having sufficient thermal stability for integrated circuit processing often include incompatible metals that must be separated from a silicon substrate. Such ferroelectric materials also tend to be strong oxygen sources, increasing the risk of undesirable oxidation of adjacent materials. Additionally, ferroelectric materials generally can only withstand a finite number of polarization reversals before their performance degrades.
Ferroelectric memories exploit the properties of ferroelectric materials. These materials are useful in semiconductor memories as they have characteristics to provide a non-volatile memory function; after a ferroelectric material has been polarized in one direction, it will hold that polarization for an extended time without further power input. In contrast, dynamic random access memory (DRAM) requires periodic refresh to maintain its data value, thus losing its data value upon the removal of its power source.
Since the physics of ferroelectric floating-gate memories are similar to standard floating-gate memories (such as Flash memories), the sensing operation is correspondingly similar. Typically, floating-gate memories are sensed by detecting the activation/deactivation of the selected transistor in response to a given gate/source voltage. Although a typical floating-gate memory""s activation/deactivation state is dependent on a stored charge of its floating gate, and a ferroelectric floating-gate memory""s activation/deactivation state is dependent on a polarization of a ferroelectric layer, they both can exhibit this binary behavior.
At the microscopic scale, the ferroelectric material can be seen to be divided into domains. A domain is a volume within which the polarization of the material is uniform. Each domain can have only two stable polarization states. The magnitude of the polarization state of the bulk material is a composite of the individual domain polarization states.
FIG. 1 schematically shows a typical hysteresis curve 12 for a ferroelectric material. When the applied electric field E is increased to a positive value E1, the polarization of the material will increase to a value P1. When the applied positive field is subsequently removed, the polarization will fall back to a positive xe2x80x9cremanent polarizationxe2x80x9d value Pr. In a similar manner, when the applied electric field is increased in the opposite direction, to a negative value xe2x88x92E2, the polarization of the material will go to a negative value xe2x88x92P2. When the applied negative field is subsequently removed, the polarization will fall back to a negative remanent polarization value xe2x88x92Pr. Thus, the material can take either of two polarization states in the absence of an electric field, depending on how it has been affected by the previously applied field. For electrical circuit analysis, the polarization state of a ferroelectric film can be thought of in terms of surface charge density, i.e., as amount of charge per unit area (usually written as xe2x80x9c"sgr"xe2x80x9d). Curve 14 is an example of a minor hysteresis curve obtained when the same material is cycled between electrical potentials having insufficient magnitude to cause complete reversal of the polarization.
When an increasingly strong electric field is applied to a ferroelectric material, more and more of the domains will change their state to line up with the applied field. The electric field seen by any one domain is affected by the polarization states of the other domains which are nearby. Consequently, a fall reversal of polarization requires not only some threshold energy level, but also some delay as individual domains align. This is inconvenient for ferroelectric memories, since it limits the write speed of any such memory. Moreover, in memories that use a destructive read, i.e., a read operation using a voltage sufficient to cause reversal of polarity, this phenomenon is also an important constraint on read access time as the data must be rewritten after sensing. This has been a problem with commercialization of ferroelectric memories, since it is highly desirable for ferroelectric memories to have access times approximately as fast as those for DRAM memories.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate architecture and methods of operation of ferroelectric semiconductor memory devices.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Depletion-mode ferroelectric transistors are described herein for use as non-volatile memory cells. Such memory cells find use in non-volatile memory devices as well as other electronic systems having non-volatile memory storage. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb, i.e., undesirable reversal of polarity. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells while avoiding undesirable reversal of polarity.
For one embodiment, the invention provides a memory cell. The memory cell includes a ferroelectric layer formed overlying a substrate and a control gate formed overlying the ferroelectric layer and coupled to a word line. The memory cell further includes a first source/drain region having a first conductivity type formed in the substrate and coupled to a program line, a second source/drain region having the first conductivity type formed in the substrate, and a channel region having the first conductivity type formed in the substrate and interposed between the first and second source/drain regions. The memory cell still further includes a diode interposed between the second source/drain region and a bit line.
For another embodiment, the invention provides a memory cell. The memory cell includes a ferroelectric layer formed overlying a substrate and a control gate formed overlying the ferroelectric layer and coupled to a word line. The memory cell further includes a first source/drain region having a first conductivity type formed in the substrate and coupled to a program line, a second source/drain region having the first conductivity type formed in the substrate, and a channel region having the first conductivity type formed in the substrate and interposed between the first and second source/drain regions. The memory cell still further includes a diode formed in the second source/drain region and interposed between the second source/drain region and a bit line.
For a further embodiment, the invention provides a memory cell. The memory cell includes a conductively-doped polysilicon layer having a first conductivity type formed overlying a substrate having the first conductivity type. The memory cell further includes a ferroelectric transistor formed overlying the polysilicon layer. The transistor has a control gate, a ferroelectric layer interposed between the polysilicon layer and the control gate, a first source/drain region having the first conductivity type formed in the polysilicon layer, a second source/drain region having the first conductivity type formed in the polysilicon layer, and a channel having the first conductivity type formed in the polysilicon layer interposed between the first and second source/drain regions. The memory cell still further includes a well region having a second conductivity type opposite the first conductivity type. The well region is interposed between the second source/drain region and the substrate.
For a further embodiment, the invention provides a method of writing to a selected ferroelectric memory cell in an array of ferroelectric memory cells. The method includes applying a programming voltage to a first word line coupled to a control gate of the selected memory cell, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell. The method further includes applying a fraction of the programming voltage to other word lines coupled to control gates of non-selected memory cells not associated with the first word line. The method still further includes applying a ground potential to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell through a diode. The method still further includes applying the fraction of the programming voltage to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled, through diodes, to second source/drain regions of non-selected memory cells not associated with the first bit line.
For yet another embodiment, the invention provides a method of reading a selected ferroelectric memory cell in an array of ferroelectric memory cells. The method includes applying a first fraction of a programming voltage to a first word line coupled to a control gate of the selected memory cell, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell. The method further includes applying a ground potential to other word lines coupled to control gates of non-selected memory cells not associated with the first word line. The method still further includes applying the first fraction of the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line. The method still further includes applying a second fraction of the programming voltage to a first bit line coupled to a second source/drain region of the selected memory cell through a diode and to other bit lines coupled, through diodes, to second source/drain regions of non-selected memory cells not associated with the first bit line.
The invention further provides apparatus, systems and methods of various scope.